Finite Impulse Response (FIR) filters have widespread use in digital communication channels requiring adaptive equalization. Applications include telecommunication systems such as Asynchronous Transfer Mode (ATM) networks and Partial Response Maximum Likelihood (PRML) read channels found in hard disk drive systems.
The early forms of such filters were generally implemented with a shift register delay line that was supplied with an input analog signal and that was provided with a plurality of taps from which there could be derived samples of the analog signal. These samples were appropriately weighted in accordance with the desired filter response and then summed to provide the desired output.
A significant disadvantage of this approach is that as the input analog sample is shifted along the register from tap to tap, errors accumulate and there tends to be substantial degradation.
To meet this problem, a solution was developed that involved storing successive analog samples only once in successive sample and hold (S/H) cells and using a rotating switch matrix to interconnect the successive S/H cells to different tap weights to simulate the shifting action of a shift register delay line. Rotating the tap weights from each S/H cell to the next requires a switch matrix that can connect every tap to every S/H cell. As the number of taps is increased to accommodate longer-duration filter impulse responses, considerable capacitance is provided at the output of each S/H cell, and this limits the maximum sampling rate that can be effectively utilized. To overcome this limitation on the sampling rate, there was proposed a solution that involved eliminating the rotating switch matrix and digitally rotating the tap weights associated with the successive S/H cells. The tap weights were implemented as Multiplying Digital to Analog Converters (MDACs), with their gain programmed by the digital tap weight stored in a shift register. Such a solution is described in a paper entitled "Design and Characterization of a Real-Time Correlator," published in the IEEE Journal of Solid-State Circuits, Vol. SC-12#6, December 1977, pp. 642-649 and "Distortion in Rotating Tap Weight Transversal Filters," published in the IEEE Journal of Solid-State Circuits, Vol. SC-14#3, June 1979, pp. 627-633, by Y. A. Hague and M. A. Copeland. The key to such described S/H and MDAC approach lies in the use of voltage, as the signal that is stored and summed, as opposed to charge, the approach that characterized previous designs. To this end, the desired tap weight is implemented with binary area-ratioed capacitors and the desired summed output is the weighted summation of the stored voltages.
However, this approach when used with a large number of weights tends to involve a substantial current drain to operate at high sample rates and so may not be readily amenable to use with low-power high-density circuits, currently characteristic of microelectronic apparatus.